Integrated circuits (ICs) are formed on semiconductor substrates using a number of different processing steps to create transistor and interconnection elements. In order to electrically connect transistor terminals associated with the semiconductor substrate, conductive (e.g., metal) vias (vertical channels) and interconnections (interconnects) are formed in dielectric (electrically insulating) materials as part of the integrated circuit. The vias and interconnects couple electrical signals and power between transistors, internal circuits of the IC, and circuits external to the IC.
Inlaid (“damascene”) interconnect processes for semiconductor devices are replacing conventional “blanket” metal deposition and etch processes. Traditionally, metal films have been deposited and patterned using photolithography techniques to form patterned metal interconnects overlying a semiconductor substrate. As interconnect geometry sizes decrease and as conductive lines are formed closer and closer together, it becomes increasingly difficult to accurately pattern the conductive lines and form the conductive interconnects using the traditional blanket deposition and patterning processes. Consequently, inlaid metal interconnect processes have been developed to overcome some of these problems.
In conventional inlaid metal interconnect processing, an interlayer dielectric (ILD) layer and a cap layer (or “hard mask” to protect the ILD layer) are deposited on an etch stop layer (ESL) overlying the semiconductor substrate. A photoresist mask is then patterned on the ILD layer and cap layers and etched to form vias or openings in the ILD layer and cap layers. The ESL formed below the ILD layer serves to stop the etch. The photoresist is then removed and another etch is performed to remove the ESL within the via prior to filling the via with metal. A blanket layer of metal, for example, copper, is then deposited across the surface to completely fill the vias. The blanket metal layer is then polished back from the surface of the ILD layer and cap layers, for example by chemical mechanical polishing (CMP), leaving the metal interconnects only in the via areas and isolated by the ILD layers.
Removing the ESL layer from the vias prior to filling them with metal with traditional inlaid etch processing creates several deleterious effects. In particular, when the ESL layer is etched from the vias, the cap layer is also etched to some degree, causing the corners of the cap layer to become rounded. The cap layer must therefore be thick enough to survive the ESL etch and protect the underlying ILD layer. Utilizing a thick cap layer, however, comes at the expense of the dielectric constant (“k”) of the “stack” (i.e., the layers of the ESL, ILD, and cap). As interconnect geometries become denser, it is important that the overall stack is composed of materials with low dielectric constants to prevent capacitance coupling and “cross talk” between interconnect patterns. Because the thickness of the cap layer depends, in part, on surviving the ESL etch, the cap layer may not be optimized to have the lowest stack dielectric constant.
Additionally, after the vias are filled with the metal layer, the surface must be polished back to the cap layer in order to remove the metal from the surface and isolate the interconnect patterns. Corner rounding of the cap layer may require additional polishing to insure isolation of the interconnect patterns. The additional polishing may damage the underlying ILD layers. As interconnect patterns become more dense, corner rounding of the cap layer leads to increasingly thick cap layers to compensate for the additional polishing needed to isolate the interconnect features. Furthermore, this increased cap thickness adds additional complications for patterning since advanced lithography processing is moving toward use of thinner resists. As a result, photoresist consumption becomes a greater concern. This issue is especially exacerbated by the need to transition from 248 nm photoresist to 193 nm photoresist, which is inherently less robust to the etch process.
Further, the ESL etch may cause ILD attack and modification of the ILD sidewalls. This attack on the ILD layer sidewalls may lead to a higher dielectric constant and decreased performance of the interconnect patterns. Also, under-layer sputtering of copper on the ILD layer sidewalls may increase electromigration and leakage of copper within the structure.
A further problem of conventional inlaid metal processing is the feature dependent loading effect during the cap and ILD etches. Certain areas, such as near the die seal or lithography alignment marks can etch significantly faster than in other areas. This difference in etch rate can lead to ESL breakthrough during the ILD etch, resulting in a build-up of charge in the areas that etch more quickly. This could result in conductor charging and explosion.
Each of these above mentioned concerns are also applicable to trench patterning in inlaid processing.
Therefore, a method and process for single inlaid processing is desired that allows for optimal thickness of the cap material to minimize the dielectric constant of the stack, requiring less polishing to isolate features and allows for the extended use of single layer photoresists. It is also desired to provide a method that minimizes ILD attack and modification, and prevents under-layer copper sputtering on the ILD sidewalls to improve the dielectric constant and electromigration performance of the stack. Further, it is desired to optimize the ESL thickness for electromigration performance, decreased stack dielectric constant, and prevent possible etch through of the ESL layer during the ILD etch.